 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| L6563 ADVANCED TRANSITION-MODE PFC CONTROLLER PRELIMINARY DATA 1 MAIN FEATURES TRANSITION-MODE CONTROL OF PFC PREREGULATORS VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION TRACKING BOOST FUNCTION PROTECTION AGAINST FEEDBACK LOOP FAILURE (LATCHED SHUTDOWN) INTERFACE FOR CASCADED CONVERTER'S PWM CONTROLLER INPUT VOLTAGE FEEDFORWARD (1/V2) REMOTE ON/OFF CONTROL LOW (90A) START-UP CURRENT 5 mA MAX. QUIESCENT CURRENT 1.5% (@ Tj = 25C) INTERNAL REFERENCE VOLTAGE -600/+800 mA TOTEM POLE GATE DRIVER WITH ACTIVE PULL-DOWN DURING UVLO SO14 PACKAGE Figure 1. Package SO14 Table 1. Order Codes Part Number L6563 L6563TR Package SO14 SO14 in Tape & Reel DESKTOP PC, SERVER, WEB SERVER IEC61000-3-2 OR JEIDA-MITI COMPLIANT SMPS, IN EXCESS OF 250W 2 DESCRIPTION 1.1 APPLICATIONS PFC PRE-REGULATORS FOR: HI-END AC-DC ADAPTER/CHARGER Figure 2. Block Diagram INV 1 TRACKING BOOST TBO 6 The device is a current-mode PFC controller operating in Transition Mode (TM). Based on the core of a standard TM PFC controller, it offers improved performance and additional functions. COMP 2 MULT 3 Ideal diode VFF 5 1 / V2 1:1 CURRENT MIRROR 1:1 BUFFER 3V MULTIPLIER LINE VOLTAGE FEEDFORWARD + 2.5V VOLTAGE REGULATOR Voltage references 1.7V LEADING-EDGE BLANKING + Q INDUCTOR SATURATION DETECTION SAT R Q UVLO COMPARA TOR 15 V 4 CS from VFF - + Vbias (INTERNAL SUPPLY BUS) VCC 14 VCC R1 GND 12 R2 S Driver 13 GD + VREF2 Starter OFF UVLO 11 ZCD 10 RUN 1.4V 0.7V - ZERO CURRENT DETECTOR STARTER 0.2V 0.3V DISABLE + LATCH Vbias SAT 9 PWM_STOP 8 PWM_LATCH FEEDBACK FAILURE DETECTION November 2004 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. - 0.52V 0.62V ON/OFF CONTROL (BROWNOUT DETECTION) + - + + PFC_OK 7 2.5V Rev. 1 1/25 L6563 2 DESCRIPTION (continued) The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @Tj = 25C) internal voltage reference. The stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/V2 correction). Additionally, the IC provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). The device features extremely low consumption (90 A before start-up and 5 mA running). An interface with the PWM controller of the DC-DC converter supplied by the PFC pre-regulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation) and to disable the PFC stage in case of light load for the DC-DC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave. In addition to an effective two-step OVP that handles normal operation overvoltages, the IC provides also a protection against feedback loop failures or erroneous output voltage setting. Table 2. Absolute Maximum Ratings Symbol Vcc ----IPWM_STOP IZCD Ptot Tj Tstg Pin 14 2, 4 to 6, 8 to 10 1, 3, 7 10 11 Parameter IC Supply voltage (Icc = 20 mA) Analog Inputs & Outputs Max. pin voltage (Ipin =1 mA) Max. sink current Zero Current Detector Max. Current Power Dissipation @Tamb = 50C Junction Temperature Operating range Storage Temperature Value self-limited -0.3 to 8 Self-limited 3 -10 (source) 10 (sink) 0.75 -25 to 150 -55 to 150 Unit V V V mA mA W C C Table 3. Thermal Data Symbol Rth j-amb Parameter Thermal Resistance, Junction-to-ambient Max. Value 120 Unit C/W Figure 3. Pin Connection (Top view) INV COMP MULT CS VFF TBO PFC_OK 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc GD GND ZCD RUN PWM_STOP PWM_LATCH 2/25 L6563 Table 4. Pin Description Pin # 1 Pin Name INV Function Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by TBO (pin #6) is activated. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET's turn-off. A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to the start-up level and asserts PWM_LATCH (pin #8) high. Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak voltage at pin MULT (#3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND. Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected between this pin and GND defines a current that is sunk from pin INV (#1). In this way, the output voltage is changed proportionally to the mains voltage (tracking boost). If this function is not used leave this pin open. PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high. Normal operation can be resumed only by cycling the Vcc. This function is used for protection in case the feedback loop fails. If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V. Output pin for fault signaling. During normal operation this pin features high impedance. If either a voltage above 2.5V at PFC_OK (pin #7) or a voltage above 1.7V on CS (pin #4) is detected the pin is asserted high. Normally, this pin is used to stop the operation of the DCDC converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM controller. If not used, the pin will be left floating. Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.5V on RUN (pin #10) the voltage at the pin is pulled to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used, the pin will be left floating. Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin #5) either directly or through a resistor divider to use this function as brownout (AC mains undervoltage) protection, tie to INV (pin #1) if the function is not used. Boost inductor's demagnetization sensing input for transition-mode operation. A negativegoing edge triggers MOSFET's turn-on. Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages. Supply Voltage of both the signal part of the IC and the gate driver. 2 3 COMP MULT 4 CS 5 VFF 6 TBO 7 PFC_OK 8 PWM_LATCH 9 PWM_STOP 10 RUN 11 12 13 ZCD GND GD 14 Vcc 3/25 L6563 Figure 4. Typical System Block Diagram PFC PRE-REGULATOR DC-DC CONVERTER Vinac Voutdc PWM is turned off in case of PFC's anomalous operation for safety L6563 PWM or Resonant CONTROLLER PFC can be turned off at light load to ease compliance with energy saving regulations. Table 5. Electrical Characteristcs (Tj = -25 to 125C, Vcc =12, Co = 1 nF between pin GD and GND, CFF =1F between pin VFF and GND; unless otherwise specified) Symbol SUPPLY VOLTAGE Vcc VccOn VccOff Hys VZ Istart-up Iq ICC Iqdis Operating range Turn-on threshold Turn-off threshold Hysteresis Zener Voltage Start-up Current Quiescent Current Operating Supply Current Idle state quiescent Current Icc = 20 mA Before turn-on, Vcc=10V After turn-on @ 70 kHz Latched by PFC_OK>Vthl or Vcs>VCSdis Disabled by PFC_OK Gain (3) 0.375 0.45 0.525 1/V 4/25 L6563 Table 5. Electrical Characteristcs (continued) (Tj = -25 to 125C, Vcc =12, Co = 1 nF between pin GD and GND, CFF =1F between pin VFF and GND; unless otherwise specified) Symbol ERROR AMPLIFIER VINV Voltage Feedback Input Threshold Line Regulation IINV Gv GB ICOMP VCOMP Input Bias Current Voltage Gain Gain-Bandwidth Product Source Current Sink Current Upper Clamp Voltage Lower Clamp Voltage CURRENT SENSE COMPARATOR ICS tLEB td(H-L) VCSclamp Vcsoffset VCSdis IOVP Hys Input Bias Current Leading Edge Blanking Delay to Output Current sense reference clamp Current sense offset IC disable level Dynamic OVP triggering current Hysteresis Static OVP threshold VOLTAGE FEEDFORWARD VVFF V VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk V ITBO Linear operation range Dropout VMULTpk-VVFF Upper Clamp Voltage Lower Clamp Voltage Arming Voltage (positive-going edge) Triggering Voltage (negative-going edge) Input Bias Current Source Current Capability Sink Current Capability Dropout voltage VVFF-VTBO Linear operation ITBO = 0.25 mA 0 IZCD = 2.5 mA IZCD = - 2.5 mA (4) (4) VZCD = 1 to 4.5 V -2.5 2.5 10 0.25 5.0 -0.3 5.7 0 1.4 0.7 1 0.3 RFF=47 k to GND 0.5 3 10 V mV V V V V A mA mA mV mA (4) (2) 2.1 VCOMP = Upper clamp, VVFF = VMULT =0.5V VMULT = 0, VVFF = 3V VMULT = 3V, VVFF = 3V (2) 1.6 17 OUTPUT OVERVOLTAGE 20 15 2.25 2.4 23 A A V 1.0 VCS = 0 100 200 120 1.08 25 5 1.7 1.8 V 1.16 -1 300 A ns ns V mV VCOMP = 4V, VINV = 2.4 V VCOMP = 4V, VINV = 2.6 V ISOURCE = 0.5 mA ISINK = 0.5 mA (2) -2 2.5 5.7 2.1 VINVCLAMP Internal clamp level Tj = 25 C 10.3 V < Vcc < 22 V (2) Vcc = 10.3 V to 22V TBO open, VINV = 0 to 4 V IINV = 1 mA Open loop 9 60 2.465 2.44 2 -0.2 9.5 80 1 -3.5 4.5 6.2 2.25 6.7 2.4 -5 2.5 2.535 2.56 5 -1 mV A V dB MHz mA mA V V V Parameter Test Condition Min. Typ. Max. Unit ZERO CURRENT DETECTOR TRACKING BOOST FUNCTION 5/25 L6563 Table 5. Electrical Characteristcs (continued) (Tj = -25 to 125C, Vcc =12, Co = 1 nF between pin GD and GND, CFF =1F between pin VFF and GND; unless otherwise specified) Symbol VTBOclamp PFC_OK Vthl Vth VEN IPFC_OK Vclamp Ileak VH PWM_STOP Ileak VL Vclamp IRUN VDIS VEN tSTART VOHdrop VOLdrop tf tr VOclamp Current Fall Time Current Rise Time Output clamp voltage UVLO saturation (1), (2) Parameters tracking each other (3) (4) V MUL T ( V CO MP - 2.5 ) The multiplier output is given by: V CS = K M ----------------------------------------------------------2 V V FF Parameters guaranteed by design, functionality tested in production. Parameter IINV-ITBO current mismatch Clamp voltage Latch-off threshold Disable threshold Enable threshold Input Bias Current Clamp voltage Low level leakage current High level High level leakage current Low level Clamp voltage Input Bias Current Disable threshold Enable threshold Start Timer period Dropout Voltage Test Condition ITBO = 25 A to 0.25 mA (2) VVFF = 4V (2) voltage rising (2) voltage falling (2) voltage rising VPFC_OK = 0 to 2.5V IPFC_OK = 1 mA VPWM_LATCH=0 IPWM_LATCH = -0.5 mA VPWM_STOP = 6V IPWM_STOP = 0.5 mA IPFC_OK = 2 mA VRUN = 0 to 3 V (2) voltage falling (2) voltage rising Min. -3.5 2.9 2.4 Typ. 3 2.5 0.2 0.26 -0.1 Max. 3.5 3.1 2.6 Unit % V V V V -1 A V 9 9.5 -1 PWM_LATCH A V 1 1 9 9.5 -1 0.5 0.57 75 IGDsource = 20 mA IGDsource = 200 mA IGDsink = 200 mA 0.52 0.6 150 2 2.5 1 30 40 IGDsource = 5mA; Vcc = 20V Vcc=0 to VccOn, Isink=10mA 10 12 0.54 0.63 300 2.6 3 2 70 80 15 1.1 A V V A V V s V V V ns ns V V 3.7 RUN FUNCTION START TIMER GATE DRIVER 6/25 L6563 3 TYPICAL ELECTRICAL PERFORMANCE Figure 8. Vcc Zener voltage vs. Tj Vccz (pin 14) (V) 28 Icc (mA) 10 5 1 0.5 0.1 0.05 0.01 0.005 0 0 5 10 15 Vcc(V) 20 25 Co = 1nF f = 70 kHz Tj = 25C Figure 5. Supply current vs. Supply voltage 27 26 25 24 23 22 -50 0 50 Tj (C) 100 150 Figure 6. IC consumption vs. Tj Icc 10 5 2 1 0.5 0.2 0.1 0.05 0.02 -50 Before start-up Vcc = 12 V Co = 1 nF f = 70 kHz Disabled or during OVP Operating Quiescent Figure 9. Feedback reference vs. Tj VREF (pin 1) (V) 2.6 Vcc = 12 V (mA) 2.55 2.5 Latched off 2.45 0 50 100 150 2.4 -50 0 50 Tj (C) 100 150 Tj (C) Figure 7. Start-up & UVLO vs. Tj 12.5 VCC-ON (V) 12 Figure 10. E/A output clamp levels vs. Tj VCOMP (pin 2) (V) 7 6 Upper clamp Vcc = 12 V 11.5 5 11 4 10.5 10 VCC-OFF 9.5 (V) 3 2 1 -50 Lower clamp 9 -50 0 50 Tj (C) 100 150 0 50 Tj (C) 100 150 7/25 L6563 Figure 11. Static OVP level vs. Tj VCOMP (pin 2) (V) Figure 14. Vcs clamp vs. Tj VCSx (pin 4) (V) 1.5 Vcc = 12 V VCOMP = Upper clamp 2.5 2.4 Vcc = 12 V 1.4 2.3 1.3 2.2 1.2 2.1 1.1 2 -50 0 50 Tj (C) 100 150 1 -50 0 50 Tj (C) 100 150 Figure 12. Dynamic OVP current vs. Tj (normalized value) IOVP Figure 15. Current-sense offset vs. mains voltage phase angle VCSoffset (pin 4) (mV) 120% Vcc = 12 V 30 Vcc = 12 V Tj = 25 25 110% 20 VMULT = 0 to 3V VFF = 3V 100% 15 10 VMULT = 0 to 0.7V VFF = 0.7V 90% 5 80% -50 0 50 Tj (C) 100 150 0 0 0.628 1.256 1.884 2.512 3.14 () Figure 13. Delay-to-output vs. Tj tD(H-L) (ns) Figure 16. IC disable level on current sense vs. Tj Vpin4 2.0 (V) 300 Vcc = 12 V Vcc = 12 V 250 1.8 200 1.6 150 1.4 100 1.2 50 -50 0 50 Tj (C) 100 150 1.0 -50 0 50 Tj (C) 100 150 8/25 L6563 Figure 17. Multiplier characteristics @ VFF=1V VCS (pin 4) VCOMP (pin 2) Figure 20. ZCD clamp levels vs. Tj VZCD (pin 11) (V) (V) 1 0.8 4.0 (V) Vcc = 12 V Tj = 25 C upper voltage clamp 5.5 5.0 4.5 7 6 5 4 3 Upper clamp Vcc = 12 V IZCD= 2.5 mA 0.6 3.5 0.4 0.2 0 3.0 2 1 0 Lower clamp 2.6 0 0.2 0.4 0.6 0.8 1 1.2 VMULT (pin 3) (V) -1 -50 0 50 Tj (C) 100 150 Figure 18. Multiplier characteristics @ VFF=3V V CS (pin 4) VCOMP (pin 2) Figure 21. ZCD source capability vs. Tj I (V) 0.5 0.4 0.3 0.2 3.5 (V) Vcc = 12 V Tj = 25 C upper voltage clamp 5.5 5.0 4.5 4.0 ZCDsrc (mA) 0 Vcc = 12 V VZCD= lower clamp -2 -4 -6 0.1 0 3.0 2.6 0 0.5 1 1.5 2 2.5 3 3.5 -8 -50 0 50 Tj (C) 100 150 VMULT (pin 3) (V) Figure 19. Multiplier gain vs. Tj KM Figure 22. VFF & TBO dropouts vs. Tj (mV) 6 1 Vcc = 12 V VCOMP =4 V VMULT = VFF =1V Vpin6 - Vpin5 0.8 4 0.6 2 0.4 Vpin5 - Vpin3 Vcc = 12 V Vpin3 = 2.9 V 0 0.2 0 -50 0 50 Tj (C) 100 150 -2 -50 0 50 Tj (C) 100 150 9/25 L6563 Figure 23. TBO current mismatch vs. Tj 100* I(INV)-I(TBO) I(INV) Figure 26. RUN thresholds vs. Tj Vpin10 (V) -0.8 -1.0 -1.2 -1.4 ITBO = 250 A Vcc = 12 V 1.0 Vcc = 12 V 0.8 0.6 ON OFF -1.6 -1.8 -2.0 ITBO = 25 A 0.4 0.2 -2.2 -2.4 -50 0 50 Tj (C) 100 150 0.0 -50 0 50 Tj (C) 100 150 Figure 24. TBO-INV current mismatch vs. TBO currents 100* I(INV)-I(TBO) I(INV) Figure 27. PWM_LATCH high saturation vs. Tj Vpin8 5.3 (V) -1.6 -1.7 -1.8 -1.9 -2.0 -2.1 -2.2 -2.3 0 100 200 300 I(TBO) Vcc = 12 V Tj = 25 C 5.2 5.1 Vcc = 12 V Isource = 50 A 5.0 4.9 4.8 4.7 4.6 400 500 600 Isource = 500 A 4.5 -50 0 50 Tj (C) 100 150 Figure 25. TBO clamp vs. Tj Vpin6 3.5 (V) Figure 28. PWM_STOP low saturation vs. Tj Vpin9 5.0 0.50 (V) 0.40 4.0 3.25 Vcc = 12 V Isink = 0.5 mA 3.0 0.30 3 2.0 0.20 2.75 Vcc = 12 V Vpin3= 4 V 1.0 0.10 0 0.0 -50 2.5 -50 0 50 Tj (C) 100 150 0 50 Tj (C) 100 150 10/25 L6563 Figure 29. PFC_OK thresholds vs. Tj Vpin7 (V) 3.0 2.0 Latch-off Vcc = 12 V Figure 32. UVLO saturation vs. Tj Vpin15 (V) 1.1 Vcc = 0 V 1 0.9 0.8 0.7 0.6 1.0 0.5 0.3 0.2 OFF ON 0.1 -50 0 50 Tj (C) 100 150 0.5 -50 0 50 Tj (C) 100 150 Figure 30. Start-up timer vs. Tj Tstart 150 (s) Vcc = 12 V Figure 33. Gate-drive output low saturation Vpin15 (V) 4 Tj = 25 C Vcc = 11 V SINK 140 3 130 2 120 1 110 100 -50 0 0 50 Tj (C) 100 150 0 200 400 600 800 1,000 IGD(mA) Figure 31. Gate-drive clamp vs. Tj Vpin15clamp (V) 12 Vcc = 20 V Figure 34. Gate-drive output high saturation Vpin15 (V) -1.5 -2 Vcc - 2.0 Vcc --2.5 2.5 Tj = 25 C Vcc = 11 V SOURCE 11.5 11 -3 Vcc - 3.0 Vcc --3.5 3.5 10.5 -4 Vcc - 4.0 -4.5 10 -50 0 100 200 300 400 500 600 700 0 50 Tj (C) 100 150 IGD (mA) 11/25 L6563 4 APPLICATION INFORMATION 4.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. Neglecting the ripple components, under steady state conditions the current through R1 equals that through R2. Considering that the non-inverting input of the error amplifier is internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then: VO - 2.5 2.5 IR2 = I R1 = ------- = --------------------- . R1 R2 If the output voltage experiences an abrupt change Vo the voltage at pin INV is kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant. Then the current through R2 remains equal to 2.5/R2 but that through R1 becomes: VO - 2.5 + V O I' R1 = --------------------------------------- . R1 The difference current IR1 = I'R1 - I'R1 = VO/R1 will flow through the compensation network and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it reaches about 18 A the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 20 A, the OVP is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 5 A. However, if the overvoltage persists (e.g. in case the load is completely disconnected), the error amplifier will eventually saturate low hence triggering an internal comparator (Static OVP) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. The output overvoltage that is able to trigger the OVP function is then: VO = R1 * 20 * 10-6 An important advantage of this technique is that the overvoltage level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 15%, which means 15% tolerance on the Vo. Since it is usually much smaller than Vo, the tolerance on the absolute value will be proportionally reduced. Example: Vo=400V, Vo=40V. Then: R1=40V/20A=2M; R2=2.5*2M*/(400-2.5)=12.58k. The tolerance on the OVP level due to the L6563 will be 40*0.15=6 V, that is 1.36%. When either OVP is activated the quiescent consumption is reduced to minimize the discharge of the Vcc capacitor. Figure 35. Output voltage setting, OVP and FFP functions: internal block diagram Vout R3 { R3a R1 R3b { R1a R1b PFC_OK 7 0.26V + + FAULT (not latched) FAULT (latched) 2.25V + + - 9.5V + E/A - Static OVP INV 1 9.5V ITBO 2.5V + Dynamic OVP TBO FUNCTION 20 A 2 COMP L6563 Frequency Compensation R4 R2 12/25 L6563 4.2 Feedback failure protection (FFP) The OVP function above described is able to handle "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails open: the voltage loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise with no control. A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 35). This divider is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected, also including worst-case load/line transients. Example: Vo = 400 V, Vox = 475 V. Select: R3=3M; then: R4=3M *2.5/(475-2.5)=15.87k. When this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 A and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltages of both the L6563 and the PWM controller go below their respective UVLO thresholds. The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at the pin go above 0.26 V. Note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator. 4.3 Voltage Feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage Feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 36). Figure 36. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic Rectified mains E/A output (VCOMP) MULTIPLIER "ideal" diode 2 Vcsx 2 current reference (Vcsx) R5 1.5 VCOMP=4V Actual Ideal + 1/V 3 MULT R6 1 9.5V L6563 5 VFF CFF RFF 0.5 0 0 0.5 1 2 VFF=VMULT 3 4 13/25 L6563 In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF); if it is too large there will be a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off is required. The L6563 realizes Voltage Feedforward with a technique that makes use of just two external parts and that limits the feedforward time constant trade-off issue to only one direction. A capacitor CFF and a resistor RFF , both connected from the VFF (#5) pin to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (#3). RFF provides a means to discharge CFF when the line voltage decreases (see Figure 36). In this way, in case of sudden line voltage rise, CFF will be rapidly charged through the low impedance of the internal diode and no appreciable overshoot will be visible at the pre-regulator's output; in case of line voltage drop CFF will be discharged with the time constant RFF*CFF, which can be in the hundred ms to achieve an acceptably low steady-state ripple and have low current distortion; consequently the output voltage can experience a considerable undershoot, like in systems with no feedforward compensation. The twice-mains-frequency (2*fL) ripple appearing across CFF is triangular with a peak-to-peak amplitude that, with good approximation, is given by: 2V MULTpk VFF = ---------------------------------------- , 1 + 4f L R FF C FF where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2*fL component, will be: 100 D 3 % = ---------------------------------2f L R FF C FF Figure 37 shows a diagram that helps choose the time constant RFF*CFF based on the amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the pin, the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 37. RFF*CFF as a function of 3rd harmonic distortion introduced in the input current 10 1 f L = 50 Hz R FF* C FF [s] 0.1 f L = 60 Hz 0.01 0.1 1 10 D3 % The dynamics of the voltage feedforward input is limited downwards at 0.5V (see Figure 36), that is the output of the multiplier will not increase any more if the voltage on the VFF pin is below 0.5V. This helps to prevent excessive power flow when the line voltage is lower than the minimum specified value 14/25 L6563 4.4 THD optimizer circuit The L6563 is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 38. THD optimization: standard TM PFC controller (left side) and L6563 (right side) Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current MOSFET's drainVdrain voltage Imains Input current Vdrain MOSFET's drain voltage Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the VFF pin (see Voltage Feedforward section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 38, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness of the optimizer circuit. 15/25 L6563 4.5 Tracking boost function In some applications it may be advantageous to regulate the output voltage of the PFC pre-regulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. This is commonly referred to as "tracking boost" or "follower boost" approach. With the L6563 this can be realized by connecting a resistor (RT) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (#1) input of the L6563's error amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC pre-regulator will be forced to get higher. Obviously, the output voltage will move in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device will regulate a fixed output voltage. Starting from the following data: Vin1 = minimum specified input RMS voltage; Vin2 = maximum specified input RMS voltage; Vo1 = regulated output voltage @ Vin = Vin1; Vo2 = regulated output voltage @ Vin = Vin2; Vox = absolute maximum limit for the regulated output voltage; Vo = OVP threshold, to set the output voltage at the desired values use the following design procedure: 1) Determine the input RMS voltage Vinclamp that produces Vo = Vox: Vox - Vo 1 Vox - Vo 2 Vin clamp = --------------------------- Vin2 - --------------------------- Vin 1 Vo 2 - Vo 1 Vo 2 - Vo 1 and choose a value Vinx such that Vin2 = Vinx < Vinclamp. This will result in a limitation of the output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp) 2) Determine the divider ratio of the MULT pin (#3) bias: 3k = ----------------------2 Vin x and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.65V. 3) Determine R1, the upper resistor of the output divider: 6 Vo R1 = ---------- 10 . 20 4) Calculate the lower resistor R2 of the output divider and the adjustment resistor RT: Vin 2 - Vin 1 R2 = 2.5 R1 --------------------------------------------------------------------------------------------------( Vo 1 - 2.5 ) Vin 2 - ( Vo 2 - 2.5 ) Vin 1 . Vin 2 - Vin1 R T = 2 k R1 -----------------------------Vo 2 - Vo 1 5) Check that the maximum current sourced by the TBO pin (#6) does not exceed the maximum specified (0.25 mA): 3 -3 ITBOmax = ------ 0.25 10 . RT In the following Mathcad(R) sheet, as an example, the calculation is shown for the circuit illustrated in Figure 39. Figure 40 shows the internal block diagram of the tracking boost function. 16/25 L6563 Design Data Vin1:=88V Vin2:=264V Vox;=400V Vo;=40V Step 1 Vox - Vo 1 Vox - Vo 2 Vin clamp : = --------------------------- Vin 2 - --------------------------- Vin 1 Vo 2 - Vo 1 Vo 2 - Vo 1 choose: Step 2 3 k: = ----------------------2 Vin x Step 3 6 Vo R1: = ---------- 10 20 Vo1:= 200V Vo2:= 385V Vinclamp = 278.27V Vinx: = 270V k = 7.857 x 10-3 R1 = 2 x 106 Step 4 Vin 2 - Vin 1 R2: = 2.5 R1 --------------------------------------------------------------------------------------------------( Vo 1 - 2.5 ) Vin 2 - ( Vo 2 - 2.5 ) Vin 1 Vin 2 - Vin 1 R T : = k 2 R1 -----------------------------Vo 2 - Vo 1 Step 5 3 3 ITBOmax : = ------ 10 RT R2 = 4.762 x 104 RT = 2.114 x 104 ITBOmax = 0.142 mA Vo(Vin1) = 200 V Vo(Vin2) = 385 V Vo(VinX) = 391.307 V Vo(Vi): = V MULTpk k 2 Vi V TBO if ( V MULTpk < 3,V MULTpk ,3 ) R1 2.5 1 + R1 + V TBO ------------ RT R2 400 Vo 2 350 Vox Vin 2 Vin x Vo ( Vin ) 300 250 200 100 150 200 Vin 250 300 17/25 L6563 Figure 39. 80W, wide-range-mains PFC pre-regulator with tracking boost function active D1 STTH1L06 T NTC Vo=200 to 385 V Po=80W Supply Voltage 10.3 to 22V R1a 3.3 M R3 68 k R5 62 k C5 1 F R8a 1 M R8b 1 M R10a 3.3 M R10b 3.3 M FUSE 4A/250V + BRIDGE 4 x 1N4007 C6 100 nF MOS STP8NM50 C1 0.22 F 400V R1b 3.3 M - 8 14 3 12 9 11 2 1 13 4 R6 10 Vac (88V to 264V) L6563 5 10 6 7 C6 56 F 400V R2 51.1 k C2 2.2nF C3 22F 25V C4 470 nF R10 390 k R4 21 k C7 10 nF R7a,b 0.68 1/4 W R9 47.5 k R11 34.8 k Figure 40. Tracking boost and Voltage Feedforward blocks Vout IR1 COMP 2 R1 2.5V INV 1 9.5V ITBO IR2 R2 1:1 CURRENT MIRROR 3V 9.5V + + - Rectified mains current reference MULTIPLIER E/A 1/V 2 R5 "ideal" diode 3 MULT R6 L6563 6 TBO ITBO RT VFF CFF RFF 5 4.6 Inductor saturation detection Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope becomes so large (50-100 times steeper, see Figure 41) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. A well-designed boost inductor must not saturate even under the worst-case operating conditions, that is at power-up with maximum load and minimum line voltage, when the error amplifier saturates high and commands the maximum peak current (defined by the current reference clamp, VCSclamp, and the sense resistor) for some line cycles. However, especially in the development stage, inductor saturation may be encountered and a protection able to prevent the application from blowing up can be very useful. The device is provided with a second comparator on the current sense pin (CS, #4) that stops and latches off the IC if the voltage on the pin, normally limited within 1.1V, exceeds 1.7V. Also the cascaded DC-DC converter can be stopped via the PWM_LATCH pin that is asserted high. In this way there can be abnormal current only for one cycle, after that the system is stopped and enabled to restart only after recycling the input power, that is when the Vcc voltages of the IC and the PWM controller go below their respective UVLO thresholds. System safety will be considerably increased. 18/25 L6563 Figure 41. Effect of boost inductor saturation on the MOSFET current and detection method Vcs 1.7V Multiplier Output IL Multiplier Output IL Vcs 1.7V Multiplier Output Vcs IL 1.7V Tdelay t Tdelay t Tdelay t Inductor not saturating Inductor slightly saturating Inductor saturating hard 4.7 Power management/housekeeping functions A special feature of this IC is that it facilitates the implementation of the "housekeeping" circuitry needed to coordinate the operation of the PFC stage to that of the cascaded DC-DC converter. The functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. This device provides some pins to do that. As already mentioned, one communication line between the IC and the PWM controller of the cascaded DC-DC converter is the PWM_LATCH pin, which is normally open when the PFC works properly and goes high if it loses control of the output voltage (because of a failure of the control loop) or if the boost inductor saturates, with the aim of latching off the PWM controller of the cascaded DC-DC converter as well ( Feedback failure protection (FFP) for more details ). A second communication line can be established via the disable function included in the PFC_OK pin ( Feedback failure protection (FFP) for more details ). Typically this line is used to allow the PWM controller of the cascaded DC-DC converter to shut down the L6563 in case of light load, to minimize the noload input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like those shown in Figure 42, where the L6563 works along with the L5991, PWM controller with standby function, can be used. Needless to say, this operation assumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in other words, that the DC-DC stage starts first, it powers both controllers and enables/disables the operation of the PFC stage. Figure 42. Interface circuits that let the L5991/ L5991A disable the L6563 at light load (slave PFC) 16 ST-BY 16 ST-BY L5991/A 4 Vref 27 k 100 nF BC557 100 k 150 k L6563 7 PFC_OK L5991/A 4 Vref 27 k Vcc L6563 14 BC557 Supply_Bus 47 k BC547 BC547 100 nF BC557 100 k 150 k 100 nF 15 k BC547 150 k 150 k The third communication line is the PWM_STOP pin (#9), which works in conjunction with the RUN pin (#10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded DC-DC converter. The pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.52V on the RUN pin. It is important to point out that this function works correctly in systems where the PFC stage is the master and the cascaded DC-DC converter is the slave or, in other words, where the PFC stage starts first, powers both controllers and enables/disables the op- 19/25 L6563 eration of the DC-DC stage. This function is quite flexible and can be used in different ways. In systems comprising an auxiliary converter and a main converter (e.g. desktop PC's silver box or hi-end LCD-TV), where the auxiliary converter also powers the controllers of the main converter, the pin RUN can be used to start and stop the main converter. In the simplest case, to enable/disable the PWM controller the PWM_STOP pin can be connected to either the output of the error amplifier (Figure 43 a) or, if the chip is provided with it, to its softstart pin (Figure 43 b). The use of the soft-start pin allows the designer to delay the start-up of the DC-DC stage with respect to that of the PFC stage, which is often desired. An underlying assumption in order for that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of the L6563. Figure 43. Interface circuits that let the L6563 switch on or off a PWM controller (master PFC) ON ON RUN OFF 10 RUN 10 L6563 9 PWM_STOP OFF L6563 9 PWM_STOP L5991/A: UC284x: UC384x: L6565: X=6 X=1 X=1 X=2 PWM controller a) X L5991/A 7 SS CSS b) If this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the DC-DC stage from starting up correctly) or, simply, the PWM controller is devoid of soft start, the arrangement of Figure 44 lets the DC-DC converter start-up when the voltage generated by the PFC stage reaches a preset value. The technique relies on the UVLO thresholds of the PWM controller. Figure 44. Interface circuits for actual power-up sequencing (master PFC) HV bus Supply rail 10 k BC337 L5991/A: X=8+9 UC284x: X=7 UC384x: X=7 L6565: X=8 L6598: X=12 X Vcc ON RUN OFF 10 14 9 PWM_STOP PFC_OK BC558C VZ1 L6563 7 VZ2 PWM controller VZ1 < UVLO, VZ2 < 9 V VZ1 + VZ2 < Vccmax Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC stage is the master) is brownout protection, thanks to the hysteresis provided. Brownout protection is basically a not-latched device shutdown function that must be activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout. 20/25 L6563 IC shutdown upon brownout can be easily realized as shown in Figure 45. The scheme on the left is of general use, the one on the right can be used if the bias levels of the multiplier and the RFF*CFF time constant are compatible with the specified brownout level and with the specified holdup time respectively. In Table 6 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Figure 45. Brownout protection (master PFC) AC mains L6563 5 RUN VFF 10 RUN 10 L6563 RFF CFF Table 6. Summary of L6563 idle states CONDITION CAUSED OR REVEALED BY PWM_LATCH (pin 8) PWM_STOP (pin9) TYPICAL IC CONSUMPTION IC behavior UVLO Feedback disconnected Saturated Boost Inductor AC Brownout Standby Vcc < 8.7 V PFC_OK > 2.5 V Vcs > 1.7 V RUN < 0.52 V PFC_OK < 0.2 V Open Active (high) Active (high) Open Open Open Open Open Active (low) Open 50 A 180 A 180 A 1.5 mA 1.5 mA Auto-restart Latched Latched Auto-restart Auto-restart 5 APPLICATION EXAMPLES AND IDEAS Figure 46. 250W, wide-range-mains PFC pre-regulator with fixed output voltage L1 D1 1N5406 D2 STTH5L06 NTC1 2.5 Vout = 400V Pout = 250 W R4 1 M R9A 1 M R9B 1 M R11A 1.87 M R11B 1.87 M R1A 820 k R1B 820 k Vcc 10.3 to 22 V R3 47 k R5 C4 6.8 k 1 F FUSE 8A/250V B1 KBU8M + C1 1 F 400V 11 C2 1 F 3 14 2 1 7 D3 1N4148 6 C8 150 F 450 V L6563 13 10 8 9 12 4 R6 33 M1 STP12NM50 C6 470 nF 630 V Vac 88V to 264V 5 R7 390 k C7 10 nF R2 10 k C3 10nF C5 470nF R8A,B 0.22 1W R10 12.7 k R12 20 k Boost Inductor (L1) Spec ETD29x16x10 core, 3C85 ferrite or equivalent 1.5 mm gap for 150 H primary inductance Primary: 74 turns 20xAWG30 ( 0.3 mm) Secondary: 8 turns 0.1 mm 21/25 L6563 Figure 47. 350W, wide-range-mains PFC pre-regulator with fixed output voltage and FOT control D1 1N5406 D2 STT H806DTI NTC1 2.5 Vout = 400V Pout = 350W L1 R4 1 M R13A 1 M R13B 1 M R15A 1.87 M R15B 1.87 M R1A 620 k R1B 620 k Vcc 10.3 to 22 V R5 C5 6.8 k 1 F FUSE 8A/250V B1 KBU8M + C1 1 F 400V 14 8 C2 1 F 3 10 5 R3 390 k R6 1.5 k TR1 BC557 9 2 1 7 D3 1N4148 6 M1A STP12NM50 C9 470 nF 630 V M1B STP12NM50 C10 10 nF C11 220 F 450 V L6563 13 11 R8 1.5 k C6 330 pF 12 4 R9 6.8 D4 1N4148 R10 6.8 R11 330 R12A,B,C 0.33 1W Vac 88V to 264V - D5 1N4148 R2 10 k C3 10nF C4 470nF R7 12 k C7 560 pF C8 330 pF R14 12.7 k R16 20 k L1: core E42*21*15, B2 material 1.9 mm air gap on centre leg, main winding inductance 0.55 mH 58 T of 20 x AWG32 ( 0.2 mm) 22/25 L6563 6 PACKAGE INFORMATION Figure 48. SO14 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 B C D (1) E e H h L k ddd 5.8 0.25 0.40 1.35 0.10 1.10 0.33 0.19 8.55 3.80 1.27 6.20 0.50 1.27 0.228 0.01 0.016 TYP. MAX. 1.75 0.30 1.65 0.51 0.25 8.75 4.0 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 0.244 0.02 0.050 TYP. MAX. 0.069 0.012 0.065 0.020 0.01 0.344 0.157 inch OUTLINE AND MECHANICAL DATA 0 (min.), 8 (max.) 0.10 0.004 (1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO14 0016019 D 23/25 L6563 7 REVISION HISTORY Table 7. Revision History Date Revision Description of Changes November 2004 1 First Issue 24/25 L6563 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 25/25 |
Price & Availability of E-L6563
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |